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LTC2754 Quad 12-/16-Bit SoftSpan IOUT DACs FEATURES
n n n n n n n n n n n
DESCRIPTION
The LTC(R)2754 is a family of quad 12- and 16-bit multiplying serial-input, current-output digital-to-analog converters. They operate from a single 3V to 5V supply and are guaranteed monotonic over temperature. The LTC2754A-16 provides full 16-bit performance (1LSB INL and DNL, max) over temperature without any adjustments. These SoftSpanTM DACs offer six output ranges (up to 10V) that can be programmed through the 3-wire SPI serial interface, or pinstrapped for operation in a single range. The content of any on-chip register (including DAC output-range settings) can be verified in just one instruction cycle; and if you change any register, that register will be automatically read back during the next instruction cycle. Voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and CLR pin both reset the DAC outputs to 0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178.
Program or Pin-Strap Six Output Ranges 0V to 5V, 0V to 10V, -2.5V to 7.5V, 2.5V, 5V, 10V Maximum 16-Bit INL Error: 1 LSB over Temperature Guaranteed Monotonic over Temperature Low Glitch Impulse 0.26nV*s (3V), 1.25nV*s (5V) Serial Readback of All On-Chip Registers Low 1A Maximum Supply Current 2.7V to 5.5V Single-Supply Operation 16-Bit Settling Time: 2s Voltage-Controlled Offset and Gain Trims Clear and Power-On-Reset to 0V Regardless of Output Range 52-Pin 7mm x 8mm QFN Package
APPLICATIONS

High Resolution Offset and Gain Adjustment Process Control and Industrial Automation Automatic Test Equipment Data Acquisition Systems
TYPICAL APPLICATION
Quad 16-Bit VOUT DAC with Software-Selectable Ranges
VREFA GEADJA RCOMA RCOMB GEADJB VREFB
REFA ROFSA
ROFSB
RINA
RINB
VDD VOSADJA IOUT2A IOUT1A RFBA
REFB
VOUTA
DAC A
DAC B
IOUT1B RFBB
INL (LSB)
SPI with READBACK RFBD IOUT1D IOUT2D VOSADJD DAC D VOUTD
LTC2754-16 RFBC DAC C IOUT2C VOSADJC REFD ROFSD GND M-SPAN RIND REFC R GEADJC COMC RCOMD ROFSC RINC
GEADJD
ALL AMPLIFIERS 1/2 LT1469
VREFD
VREFC
2754 TA01
+ -
IOUT1C
- +
- + + -
- + + -
LTC2754-16 Integral Nonlinearity (INL)
1.0 VOSADJB IOUT2B VOUTB 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2754 G01
VDD = 5V VREF = 5V 10V RANGE
- + + -
VOUTC
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LTC2754 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW VOSADJA VOSADJB RCOMA RCOMB 40 GEADJB 39 RINB 38 IOUT2B 37 GND 36 LDAC 35 S2 53 34 S1 33 S0 32 M-SPAN 31 RFLAG 30 CLR 29 IOUT2C 28 RINC 27 GEADJC 15 16 17 18 19 20 21 22 23 24 25 26 ROFSD VOSADJD VOSADJC ROFSC RCOMD RCOMC REFD RFBD IOUT1D IOUT1C RFBC REFC IOUT1A IOUT1B ROFSA ROFSB REFB REFA RFBA RFBB
IOUT1X , IOUT2X to GND ............................................0.3V RINX, RCOMX , REFX, RFBX , ROFSX , VOSADJX , GEADJX to GND ........................................................18V VDD to GND .................................................. -0.3V to 7V Digital Inputs and Outputs to GND ................ -0.3V to VDD+0.3V (max 7V) Operating Temperature Range LTC2754C ................................................ 0C to 70C LTC2754I..............................................-40C to 85C Maximum Junction Temperature........................... 150C Storage Temperature Range...................-65C to 150C
52 51 50 49 48 47 46 45 44 43 42 41 GEADJA 1 RINA 2 IOUT2A 3 GND 4 CS/LD 5 SDI 6 SCK 7 SRO 8 SROGND 9 VDD 10 GND 11 IOUT2D 12 RIND 13 GEADJD 14
UKG PACKAGE 52-LEAD (7mm 8mm) PLASTIC QFN TJMAX = 150C, JA = 29C/W EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2754CUKG-12#PBF LTC2754IUKG-12#PBF LTC2754BIUKG-16#PBF LTC2754AIUKG-16#PBF TAPE AND REEL LTC2754CUKG-12#TRPBF LTC2754IUKG-12#TRPBF LTC2754BIUKG-16#TRPBF LTC2754AIUKG-16#TRPBF PART MARKING* LTC2754UKG-12 LTC2754UKG-12 LTC2754UKG-16 LTC2754UKG-16 LTC2754UKG-16 LTC2754UKG-16 PACKAGE DESCRIPTION 52-Lead (7mm x 8mm) Plastic QFN 52-Lead (7mm x 8mm) Plastic QFN 52-Lead (7mm x 8mm) Plastic QFN 52-Lead (7mm x 8mm) Plastic QFN 52-Lead (7mm x 8mm) Plastic QFN 52-Lead (7mm x 8mm) Plastic QFN TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C 0C to 70C -40C to 85C
LTC2754BCUKG-16#PBF LTC2754BCUKG-16#TRPBF LTC2754ACUKG-16#PBF LTC2754ACUKG-16#TRPBF
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC2754 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Resolution Monotonicity DNL INL GE Differential Nonlinearity Integral Nonlinearity Gain Error Gain Error Temperature Coefficient BZE Bipolar Zero Error Bipolar Zero Temperature Coefficient PSR ILKG Power Supply Rejection VDD = 5V, 10% VDD = 3V, 10%

VDD = 5V, VREF = 5V unless otherwise specified. The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS

MIN 12 12
LTC2754-12 TYP MAX
MIN 16 16
LTC2754B-16 TYP MAX
MIN 16 16
LTC2754A-16 TYP MAX
UNITS Bits Bits
Static Performance
1 1 0.5 1 2 1 1 0.5 0.025 0.06 0.05 2 5 0.05
1 2 20
0.2 0.4 2 1
1 1 12
LSB LSB LSB ppm/C
All Output Ranges Gain/Temp All Bipolar Ranges
0.2 0.5
12
1 0.5
8
LSB ppm/C
0.4 1 2 5
0.03 0.1 0.05
0.2 0.5 2 5
LSB/V LSB/V nA nA
IOUT1 Leakage Current TA = 25C TMIN to TMAX
VDD = 5V, VREF = 5V unless otherwise specified. The denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL Analog Pins Reference Inverting Resistors RREF RFB ROFS RVOSADJ RGEADJ CIOUT1 DAC Input Resistance Feedback Resistors Bipolar Offset Resistors Offset Adjust Resistors Gain Adjust Resistors Output Capacitance Full-Scale Zero-Scale 0V to 10V Range, 10V Step. To 0.0015% FS (Note 5) VDD = 5V (Note 6) VDD = 3V (Note 6) (Note 7) 0V to 5V Range, VREF = 3VRMS, Code = Full Scale, -3dB BW 0V to 5V Range, VREF = 10V, 10kHz Sine Wave (Note 8) (Note 9) Multiplying (Note 10) at IOUT1 (Note 3) (Note 3) (Note 4)

PARAMETER
CONDITIONS
MIN 16 8 8 16 1024 2048
TYP 20 10 10 20 1280 2560 75 45 2 1.25 0.26 2 2 0.5 -109 -110 13
MAX
UNITS k k k k k k pF
Dynamic Performance Output Settling Time Glitch Impulse Digital-to-Analog Glitch Impulse Reference Multiplying BW Multiplying Feedthrough Error Analog Crosstalk THD Total Harmonic Distortion Output Noise Voltage Density s nV*s nV*s nV*s MHz mV dB dB nV/Hz
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LTC2754 ELECTRICAL CHARACTERISTICS
SYMBOL Power Supply VDD IDD Digital Inputs VIH VIL Digital Input High Voltage Digital Input Low Voltage Hysteresis Voltage IIN CIN Digital Outputs VOH VOL IOH = 200A IOL = 200A 2.7V VDD 5.5V 2.7V VDD 5.5V

VDD = 5V, VREF = 5V unless otherwise specified. The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
PARAMETER Supply Voltage Supply Current, VDD Digital Inputs = 0V or VDD 3.3V VDD 5.5V 2.7V VDD < 3.3V 4.5V < VDD 5.5V 2.7V VDD 4.5V VIN = GND to VDD VIN = 0V (Note 11) CONDITIONS

MIN 2.7
TYP
MAX 5.5
UNITS V A V V
0.5 2.4 2
1

0.8 0.6 0.1 1 6 VDD - 0.4 0.4
V V V A pF V V
Digital Input Current Digital Input Capacitance

TIMING CHARACTERISTICS
otherwise specifications are at TA = 25C.
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 PARAMETER SDI Valid to SCK Set-Up SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High CS/LD Low to SCK Positive Edge CS/LD High to SCK Positive Edge SRO Propagation Delay CLR Pulse Width Low LDAC Pulse Width Low CLR Low to RFLAG Low CS/LD High to RFLAG High SCK Frequency VDD = 2.7V to 3.3V t1 t2 t3 t4 t5 t6 SDI Valid to SCK Set-Up SDI Valid to SCK Hold SCK High Time SCK Low Time CS/LD Pulse Width LSB SCK High to CS/LD High VDD = 4.5V to 5.5V
The denotes specifications that apply over the full operating temperature range,
CONDITIONS

MIN 7 7 11 11 9 4 4 4
TYP
MAX
UNITS ns ns ns ns ns ns ns ns
CLOAD = 10pF

18 36 15 50 40 40 9 9 15 15 12 5
ns ns ns ns ns MHz ns ns ns ns ns ns
CLOAD = 10pF (Note 11) CLOAD = 10pF (Note 11) 50% Duty Cycle (Note 12)

(Note 11) CL = 10pF

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LTC2754 TIMING CHARACTERISTICS
otherwise specifications are at TA = 25C.
PARAMETER CS/LD Low to SCK Positive Edge CS/LD High to SCK Positive Edge SRO Propagation Delay CLR Pulse Width Low LDAC Pulse Width Low CLR Low to RFLAG Low CS/LD High to RFLAG high SCK Frequency CLOAD = 10pF (Note 11) CLOAD = 10pF (Note 11) 50% Duty Cycle (Note 12) CLOAD = 10pF SYMBOL t7 t8 t9 t10 t11 t12 t13
The denotes specifications that apply over the full operating temperature range,
CONDITIONS

MIN 5 5
TYP
MAX
UNITS ns ns
26 60 20 70 60 25
ns ns ns ns ns MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Because of the proprietary SoftSpan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the IOUT1X and IOUT2X pins are held at ground. Note 4: Input resistors measured from RINX to RCOMX ; feedback resistors measured from RCOMX to REFX. Note 5: Using LT1469 with CFEEDBACK = 15pF. A 0.0015% settling time of 1.7s can be achieved by optimizing the time constant on an individual basis. See Application Note 74, Component and Measurement Advances Ensure 16-Bit DAC Settling Time. Note 6: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V. Note 8. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA , expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave. Crosstalk between other DAC channels is similar or better. Note 9. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1469. Note 10. Calculation from Vn = 4kTRB, where k = 1.38E-23 J/K (Boltzmann constant), R = resistance (), T = temperature (K), and B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale. Note 11. Guaranteed by design, not subject to test. Note 12. When using SRO, maximum SCK frequency fMAX is limited by SRO propagation delay t9 as follows: 1 fMAX = 2 (t + t ) , where t is the setup time of the receiving device. S 9 S
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2754-16 Integral Nonlinearity (INL)
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2754 G01
TA = 25C, unless otherwise noted.
Differential Nonlinearity (DNL)
1.0 1.0 VDD = 5V VREF = 5V 10V RANGE 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 16384 32768 CODE 49152 65535
2754 G02
INL vs Temperature
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 20 40 0 60 TEMPERATURE (C) 80
2754 G03
VDD = 5V VREF = 5V 10V RANGE
+INL
-INL
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LTC2754 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2754-16 DNL vs Temperature
VDD = 5V 0.8 VREF = 5V 10V RANGE 0.6 0.4 DNL (LSB) BZE (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 20 40 0 60 TEMPERATURE (C) 80
2754 G04
TA = 25C, unless otherwise noted.
Bipolar Zero vs Temperature
8 6 4 2 0.5ppm/C (TYP) 0 -2 -4 -6 -8 -40 -20 40 60 20 TEMPERATURE (C) 0 80
2754 G05
Gain Error vs Temperature
16 12 8 GE (LSB) 4 1ppm/C (TYP) 0 -4 -8 -12 -16 -40 -20 0 40 60 20 TEMPERATURE (C) 80
2754 G06
1.0
VDD = 5V VREF = 5V 10V RANGE
VDD = 5V VREF = 5V 10V RANGE
+DNL -DNL
INL vs VREF
1.0 VDD = 5V 0.8 5V RANGE 0.6 0.4 INL (LSB) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -10 -8 -6 4 202 VREF (V) 4 6 8 10 -INL +INL +INL 1.0
DNL vs VREF
VDD = 5V 0.8 5V RANGE 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -10 -8 -6 4 202 VREF (V) 4 6 8 10 +DNL -DNL +DNL -DNL
-INL
2754 G07
2754 G08
INL vs VDD
1.0 0.8 0.6 +INL ATTENUATION (dB) 0.4 INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3 3.5 4 VDD (V)
2754 G09
Multiplying Frequency Response vs Digital Code
0 -20 -40 -60 -80
ALL BITS ON D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
-INL
-100
UNIPOLAR 5V OUTPUT RANGE LT1469 OUTPUT AMPLIFIER CFEEDBACK = 8.2pF ALL BITS OFF
4.5
5
5.5
-120 100
1k
10k 100k FREQUENCY (Hz)
1M
10M
2754 G10
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LTC2754 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2754-12 Integral Nonlinearity (INL)
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2754 G11
TA = 25C, unless otherwise noted.
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 1024 2048 CODE 3072 4095
2754 G12
VDD = 5V VREF = 5V 10V RANGE
VDD = 5V VREF = 5V 10V RANGE
LTC2754 Supply Current vs Logic Input Voltage
5 CLR, LDAC, SDI, SCK, CS/LD TIED TOGETHER LOGIC THRESHOLD (V)
Logic Threshold vs Supply Voltage
2 1.75 1.5 1.25 FALLING 1 0.75 RISING SUPPLY CURRENT (mA) 100 10 1 0.1
Supply Current vs Clock Frequency
4 SUPPLY CURRENT (mA)
3
VDD = 5V VDD = 3V
2 VDD = 5V 1 VDD = 3V 0 0 1 3 4 2 DIGITAL INPUT VOLTAGE (V) 5
2754 G13
0.01 0.001
0.5
2.5
3
3.5
4 VDD (V)
4.5
5
5.5
2754 G14
0.0001 1 100 10k 1M SCK FREQUENCY (Hz) 100M
2754 G15
Midscale Glitch
CS/LD 2V/DIV CS/LD 5V/DIV 0.26nV*s TYP VOUT 5mV/DIV
Midscale Glitch
Settling 0V to 10V
CS/LD 5V/DIV 1.25nV*s TYP GATED SETTLING WAVEFORM 250V/DIV
VOUT 5mV/DIV
VDD = 3V 500ns/DIV VREF = 5V 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 27pF
2754 G16
VDD = 5V 500ns/DIV VREF = 5V 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 27pF
2754 G17
500ns/DIV USING LT1469 AMP CFEEDBACK = 12pF 0V TO 10V STEP
2754 G17
RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER
RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER
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LTC2754 PIN FUNCTIONS
GEADJA (Pin1): Gain Adjust Pin for DAC A. This control pin can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 512 LSB (LTC2754-16) for a voltage input range of VRINA (i.e., 5V for a 5V reference input). Tie to ground if not used. RINA (Pin 2): Input Resistor for Reference Inverting Amplifier. The 20k input resistor is connected internally from RINA to RCOMA. For normal operation tie RINA to the external reference voltage VREFA (see Typical Applications). Any or all of these precision-matched resistor sets (Each set comprising RINX, RCOMX and REFX) may be used to invert one or more positive reference voltages to the negative voltages needed by the DACs. Typically 5V; accepts up to 15V. IOUT2A (Pin 3): DAC A Current Output Complement. Tie IOUT2A to ground. GND (Pin 4): Ground; provides shielding for IOUT2A. Tie to ground. CS/LD (Pin 5): Synchronous Chip Select and Load Pin. SDI (Pin 6): Serial Data Input. Data is clocked in on the rising edge of the serial clock (SCK) when CS/LD is low. SCK (Pin 7): Serial Clock. SRO (Pin 8): Serial Readback Output. Data is clocked out on the falling edge of SCK. Readback data begins clocking out after the last address bit A0 is clocked in. SRO is an active output only when the chip is selected (i.e., when CS/LD is low). Otherwise SRO presents a high-impedance output in order to allow other parts to control the bus. SROGND (Pin 9): Ground pin for SRO. Tie to ground. VDD (Pin 10): Positive Supply Input; 2.7V VDD 5.5V. Bypass with a 0.1F low-ESR ceramic capacitor to ground. GND (Pin 11): Ground. Tie to ground. IOUT2D (Pin 12): DAC D Current Output Complement. Tie IOUT2D to ground. RIND (Pin 13): Input Resistor for Reference Inverting Amplifier. The 20k input resistor is connected internally from RIND to RCOMD. For normal operation tie RIND to the external reference voltage VREFD (see Typical Applications). Any or all of these precision-matched resistor sets (Each set comprising RINX, RCOMX and REFX) may be used to invert one or more positive reference voltages to the negative voltages needed by the DACs. Typically 5V; accepts up to 15V. GEADJD (Pin 14): Gain Adjust Pin for DAC D. This control pin can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 512 LSB (LTC2754-16) for a voltage input range of VRIND (i.e., 5V for a 5V reference input). Tie to ground if not used. RCOMD (Pin 15): Center Tap Point for Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RIND to RCOMD and from RCOMD to REFD, respectively (see Block Diagram). For normal operation tie RCOMD to the negative input of external reference inverting amplifier (see Typical Applications). REFD (Pin 16): Inverted Reference Voltage for DAC D, with internal connection to the reference inverting resistor. The 20k resistor is connected internally from REFD to RCOMD . For normal operation tie this pin to the output of reference inverting amplifier (see Typical Applications). Typically -5V; accepts up to 15V. The impedance looking into this pin is 10k to ground (RIND and RCOMD floating). ROFSD (Pin 17): Bipolar Offset Network for DAC D. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; for normal operation tie to the positive reference voltage at RIND (Pin 13). The impedance looking into this pin is 20k to ground. RFBD (Pin 18): DAC D Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC D (see Typical Applications). The DAC output current from IOUT1D flows through the feedback resistor to the RFBD pin. The impedance looking into this pin is 10k to ground. IOUT1D (Pin 19): DAC D Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC D (see Typical Applications).
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LTC2754 PIN FUNCTIONS
VOSADJD (Pin 20): DAC D Offset Adjust Pin. This control pin can be used to null unipolar offset or bipolar zero error. The offset voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJD produces VOS = -512 LSB (LTC2754-16) in any output range (assumes a 5V reference voltage at RIND). Tie to ground if not used. VOSADJC (Pin 21): DAC C Offset Adjust Pin. This control pin can be used to null unipolar offset or bipolar zero error. The offset voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJC produces VOS = -512 LSB (LTC2754-16) in any output range (assumes a 5V reference voltage at RINC). Tie to ground if not used. IOUT1C (Pin 22): DAC C Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC C (see Typical Applications). RFBC (Pin 23): DAC C Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC C (see Typical Applications). The DAC output current from IOUT1D flows through the feedback resistor to the RFBC pin. The impedance looking into this pin is 10k to ground. ROFSC (Pin 24): Bipolar Offset Network for DAC C. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; for normal operation tie to the positive reference voltage at RINC (Pin 28). The impedance looking into this pin is 20k to ground. REFC (Pin 25): Inverted Reference Voltage for DAC C, with internal connection to the reference inverting resistor. The 20k resistor is connected internally from REFC to RCOMC. For normal operation tie this pin to the output of reference inverting amplifier (see Typical Applications). Typically -5V; accepts up to 15V. The impedance looking into this pin is 10k to ground (RINC and RCOMC floating). RCOMC (Pin 26): Center Tap Point for Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINC to RCOMC and from RCOMC to REFC, respectively (see Block Diagram). For normal operation tie RCOMC to the negative input of external reference inverting amplifier (see Typical Applications). GEADJC (Pin 27): Gain Adjust Pin for DAC C. This control pin can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 512 LSB (LTC2754-16) for a voltage input range of VRINC (i.e., 5V for a 5V reference input). Tie to ground if not used. RINC (Pin 28): Input Resistor for Reference Inverting Amplifier. The 20k input resistor is connected internally from RINC to RCOMC. For normal operation tie RINC to the external reference voltage VREFC (see Typical Applications). Any or all of these precision-matched resistor sets (Each set comprising RINX, RCOMX and REFX) may be used to invert one or more positive reference voltages to the negative voltages needed by the DACs. Typically 5V; accepts up to 15V. IOUT2C (Pin 29): DAC C Current Output Complement. Tie IOUT2C to ground. CLR (Pin 30): Asynchronous Clear Pin. When this pin is low, all DAC registers (both code and span) are cleared to zero. All DAC outputs are cleared to zero volts. RFLAG (Pin 31): Reset Flag Pin. An active low output is asserted when there is a power-on reset or a clear event. Returns high when an Update command is executed. M-SPAN (Pin 32): Manual Span Control Pin. M-SPAN is used in conjunction with pins S2, S1 and S0 (Pins 33, 34 and 35) to configure all DACs for operation in a single, fixed output range. To configure the part for manual-span use, tie M-SPAN directly to VDD . The active output range is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. To configure the part for SoftSpan use, tie M-SPAN directly to GND. The output ranges are then individually and dynamically controllable through the SPI port; and pins S2, S1 and S0 have no effect. See `Manual Span Configuration' in the Operation section. M-SPAN must be connected either directly to GND (SoftSpan configuration) or to VDD (manual-span configuration).
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LTC2754 PIN FUNCTIONS
S0 (Pin 33): Span Bit 0. In Manual Span mode (M-SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. S1 (Pin 34): Span Bit 1. In Manual Span mode (M-SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. S2 (Pin 35): Span Bit 2. In Manual Span mode (M-SPAN tied to VDD), Pins S0, S1 and S2 are pin-strapped to select a single fixed output range for all DACs. These pins should be tied to either GND or VDD even if they are unused. LDAC (Pin 36): Asynchronous DAC Load Input. When LDAC is a logic low, all DACs are updated (CS/LD must be high). GND (Pin 37): Ground; provides shielding for IOUT2B. Tie to ground. IOUT2B (Pin 38): DAC B Current Output Complement. Tie IOUT2B to ground. RINB (Pin 39): Input Resistor for Reference Inverting Amplifier. The 20k input resistor is connected internally from RINB to RCOMB . For normal operation tie RINB to the external reference voltage VREFB (see Typical Applications). Any or all of these precision-matched resistor sets (Each set comprising RINX , RCOMX and REFX) may be used to invert one or more positive reference voltages to the negative voltages needed by the DACs. Typically 5V; accepts up to 15V. GEADJB (Pin 40): Gain Adjust Pin for DAC B. This control pin can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 512 LSB (LTC2754-16) for a voltage input range of VRINB (i.e., 5V for a 5V reference input). Tie to ground if not used. RCOMB (Pin 41): Center Tap Point for Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINB to RCOMB and from RCOMB to REFB, respectively (see Block Diagram). For normal operation tie RCOMB to the negative input of external reference inverting amplifier (see Typical Applications). REFB (Pin 42): Inverted Reference Voltage for DAC B, with internal connection to the reference inverting resistor. The 20k resistor is connected internally from REFB to RCOMB . For normal operation tie this pin to the output of reference inverting amplifier (see Typical Applications). Typically -5V; accepts up to 15V. The impedance looking into this pin is 10k to ground (RINB and RCOMB floating). ROFSB (Pin 43): Bipolar Offset Network for DAC B. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; for normal operation tie to the positive reference voltage at RINB (Pin 39). The impedance looking into this pin is 20k to ground. RFBB (Pin 44): DAC B Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC B (see Typical Applications). The DAC output current from IOUT1B flows through the feedback resistor to the RFBB pin. The impedance looking into this pin is 10k to ground. IOUT1B (Pin 45): DAC B Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC B (see Typical Applications). VOSADJB (Pin 46): DAC B Offset Adjust Pin. This control pin can be used to null unipolar offset or bipolar zero error. The offset-voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJB produces VOS = -512 LSB (LTC2754-16) in any output range (assumes a 5V reference voltage at RINB). Tie to ground if not used. VOSADJA (Pin 47): DAC A Offset Adjust Pin. This control pin can be used to null unipolar offset or bipolar zero error. The offset-voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJA produces VOS = -512 LSB (LTC2754-16) in any output range (assumes a 5V reference voltage at RINA). Tie to ground if not used. IOUT1A (Pin 48): DAC A Current Output. This pin is a virtual ground when the DAC is operating and should reside at 0V. For normal operation tie to the negative input of the I/V converter amplifier for DAC A (see Typical Applications). RFBA (Pin 49): DAC A Feedback Resistor. For normal operation tie to the output of the I/V converter amplifier for DAC A (see Typical Applications). The DAC output current from IOUT1A flows through the feedback resistor to the RFBA pin. The impedance looking into this pin is 10k to ground.
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10
LTC2754 PIN FUNCTIONS
ROFSA (Pin 50): Bipolar Offset Network for DAC A. This pin provides the translation of the output voltage range for bipolar spans. Accepts up to 15V; for normal operation tie to the positive reference voltage at RINA (Pin 2). The impedance looking into this pin is 20k to ground. REFA (Pin 51): Inverted Reference Voltage for DAC A, with internal connection to the reference inverting resistor. The 20k resistor is connected internally from REFA to RCOMA. For normal operation tie this pin to the output of reference inverting amplifier (see Typical Applications). Typically -5V; accepts up to 15V. The impedance looking into this pin is 10k to ground (RINA and RCOMA floating). RCOMA (Pin 52): Center Tap Point for Reference Amplifier Inverting Resistors. The 20k reference inverting resistors are connected internally from RINA to RCOMA and from RCOMA to REFA, respectively (see Block Diagram). For normal operation tie RCOMA to the negative input of external reference inverting amplifier (see Typical Applications). Exposed Pad (Pin 53): Ground. The Exposed Pad must be soldered to the PCB.
BLOCK DIAGRAM
10 RINA 2 GEADJA 1 RCOMA 52 20k REFA 51 ROFSA 50 RFBA 49 IOUT1A 48 IOUT2A 3 DAC A 16-BIT WITH SPAN SELECT 16 DATA REGISTERS DAC REG 3 INPUT REG DATA REGISTERS INPUT REG DAC REG 3 16 DAC B 16-BIT WITH SPAN SELECT VDD
2.56M 20k LTC2754-16 20k 20k
2.56M
39 RINB 40 GEADJB 41 RCOMB
42 REFB 43 ROFSB 44 RFBB 45 IOUT1B 38 IOUT2B
SPAN REGISTERS DAC REG INPUT REG
SPAN REGISTERS INPUT REG DAC REG
VOSADJA 47 VOSADJD 20 16 IOUT2D 12 IOUT1D 19 RFBD 18 ROFSD 17 REFD 16 20k RCOMD 15 GEADJD 14 RIND 13 2.56M 20k CONTROL AND READBACK LOGIC 20k POWER-ON RESET DAC D 16-BIT WITH SPAN SELECT DATA REGISTERS DAC REG 3 INPUT REG DATA REGISTERS INPUT REG DAC REG 3 16 DAC B C 16-BIT WITH SPAN SELECT
46 VOSADJB 21 VOSADJC
29 IOUT2C 22 IOUT1C 23 RFBC 24 ROFSC 25 REFC
SPAN REGISTERS DAC REG INPUT REG
SPAN REGISTERS INPUT REG DAC REG
20k 2.56M 26 RCOMC 27 GEADJC 28 RINC
4, 11, 37 32 GND 35 34 33 S0 31 RFLAG 30 CLR 5 6 7 36 8 9 M-SPAN S2 S1 CS/LD SDI SCK LDAC SRO
2754 BD
SROGND
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11
LTC2754 TIMING DIAGRAMS
t1 t2 SCK 1 t3 2 t4 31 t6 32 t8 SDI t5 CS/LD t11 LDAC t9 SRO Hi-Z LSB
2754 TD
LSB t7
OPERATION
Output Ranges The LTC2754 is a quad, current-output, serial-input precision multiplying DAC with selectable output ranges. Ranges can either be programmed in software for maximum flexibility--each of the four DACs can be programmed to any one of six output ranges--or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (2.5V, 5V, 10V and -2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. When a reference voltage of 2V is used, the ranges become: 0V to 2V, 0V to 4V, 1V, 2V, 4V and -1V to 3V. The output ranges are linearly scaled for other reference voltages. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2754 to operate in a single span without additional operational overhead, tie the M-SPAN pin directly to VDD. The active output range for all four DACs is then set via hardware pin strapping of pins S2, S1 and S0 (rather than through the SPI port); and Write and Update commands have no effect on the active output span. See Figure 1 and Table 3. Tie the M-SPAN pin to ground for normal SoftSpan operation.
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VDD
LTC2754-16
VDD DAC A
M-SPAN S2 S1 S0 DAC B
- + - + - + - +
2754 F01
10V
10V
DAC C
10V
DAC D CS/LD SDI SCK
10V
Figure 1. Using M-SPAN to Configure the LTC2754 for Single-Span Operation (10V Range Shown).
12
LTC2754 OPERATION
Input and DAC Registers The LTC2754 has 5 internal registers for each DAC, a total of 20 registers (see Block Diagram). Each DAC channel has two sets of double-buffered registers--one set for the code data, and one for the output range of the DAC--plus one readback register. Double buffering provides the capability to simultaneously update the span (output range) and code, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs. Each set of double-buffered registers comprises an Input register and a DAC register. Input register: The Write operation shifts data from the SDI pin into a chosen Input register. The Input registers are holding buffers; Write operations do not affect the DAC outputs. DAC register: The Update operation copies the contents of an Input register to its associated DAC register. The contents of a DAC register directly updates the associated DAC output voltage or output range. Note that updates always include both Data and Span registers; but the values held in the DAC registers will only change if the associated Input register values have previously been changed via a Write operation. Serial Interface When the CS/LD pin is taken low, the data on the SDI pin is loaded into the shift register on the rising edge of the clock (SCK pin). The minimum (24-bit wide) loading sequence required for the LTC2754 is a 4-bit command word (C3 C2 C1 C0), followed by a 4-bit address word (A3 A2 A1 A0) and 16 data (span or code) bits, MSB first. Figure 2 shows the SDI input word syntax to use when writing code or span. If a 32-bit input sequence is used, the first eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. Figure 3 shows the input and readback sequences for both 24-bit and 32-bit operations. When CS/LD is low, the SRO pin (Serial Readback Output) is an active output.The readback data begins after the command (C3-C0) and address (A3-A0) words have been shifted into SDI. SRO outputs a logic low until the readback data begins. For a 24-bit input sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. For a 32-bit sequence, the bits are shifted out on clocks 16-31; see Figure 3b. When CS/LD is high, the SRO pin presents a high impedance (three-state) output. LDAC is an asynchronous update pin. When LDAC is taken low, all DACs are updated with code and span data (data in the Input buffers is copied into the DAC buffers). CS/LD must be high during this operation; otherwise LDAC is locked out and will have no effect. The use of LDAC is functionally identical to the "Update All DACs" serial input command. The codes for the command word (C3-C0) are defined in Table 1; Table 2 defines the codes for the address word (A3-A0). Readback In addition to the Input and DAC registers, each DAC has one Readback register associated with it. When a Read command is issued to a DAC, the contents of one of its four buffers (Input and DAC registers for each of Span and Code) is copied into its Readback register and serially shifted out through the SRO pin. Figure 3 shows the loading and readback sequences. In the data field (D15-D0) of any non-read instruction cycle, SRO shifts out the contents of the buffer that was specified in the preceding command. This "rolling readback" default mode of operation can dramatically reduce the number of instruction cycles needed, since any command can be verified during succeeding commands with no additional overhead. See Figure 4. Table 1 shows the storage location (`readback pointer') of the data which will be output from SRO during the next instruction. For Read commands, the data is shifted out during the Read instruction itself (on the 16 falling SCK edges immediately after the last address bit is shifted in on SDI). When checking the span of a DAC using SRO, the span bits are the last four bits shifted out, corresponding to their sequence and positions when writing a span. See Figure 3.
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13
LTC2754 OPERATION
Table 1. Command Codes
C3 0 0 0 0 0 0 1 1 1 1 1 1 1 CODE C2 C1 0 0 1 1 1 1 0 0 0 0 1 1 1 - - 1 1 0 0 1 1 0 0 1 1 0 0 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 1 COMMAND Write Span DAC n Write Code DAC n Update DAC n Update All DACs Write Span DAC n Update DAC n Write Code DAC n Update DAC n Write Span DAC n Update All DACs Write Code DAC n Update All DACs Read Input Span Register DAC n Read Input Code Register DAC n Read DAC Span Register DAC n Read DAC Code Register DAC n No Operation System Clear Initial Power-Up or Power Interupt - - READBACK POINTER- CURRENT INPUT WORD W0 Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command Set by Previous Command READBACK POINTER- NEXT INPUT WORD W+1 Input Span Register DAC n Input Code Register DAC n DAC Span Register DAC n DAC Code Register DAC A DAC Span Register DAC n DAC Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n
Input Span Register DAC n Input Code Register DAC n DAC Span Register DAC n DAC Code Register DAC n Set by Previous Command DAC Code Register DAC n DAC Span Register DAC A DAC Span Register DAC A
Codes not shown are reserved-do not use
Table 2. Address Codes A3
0 0 0 0 1
Table 3. Span Codes n
DAC A DAC B DAC C DAC D All DACs (Note 1)
A2
0 0 1 1 1
A1
0 1 0 1 1
A0
x x x x x
S3
x x x x x x
S2
0 0 0 0 1 1
S1
0 0 1 1 0 0
S0
0 1 0 1 0 1
SPAN
Unipolar 0V to 5V Unipolar 0V to 10V Bipolar -5V to 5V Bipolar -10V to 10V Bipolar -2.5V to 2.5V Bipolar -2.5V to 7.5V
Codes not shown are reserved-do not use. x = Don't Care. Note 1. If readback is taken using the All DACs address, the LTC2754 defaults to DAC A.
Codes not shown are reserved-do not use. x = Don't Care.
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14
LTC2754 OPERATION
Readback in M-Span Configuration If the part is in M-Span configuration and a DAC Span register is specified for readback, then the data shifted out of SRO will reflect the actual active span. The hardwareconfigured output range is therefore software detectable and available for use in programming. Examples 1. Using a 24-bit instruction, load DAC A with the unipolar range of 0V to 10V, output at zero volts and all other DACs with the bipolar range of 10V, outputs at zero volts. Note all DAC outputs should change at the same time. a) CS/LD Clock SDI = 0010 1111 0000 0000 0000 0011 b) CS/LD Input register- Range of all DACs set to bipolar 10V. c) CS/LD Clock SDI = 0010 0000 0000 0000 0000 0001 d) CS/LD Input register- Range of DAC A set to unipolar 0V to 10V. e) CS/LD Clock SDI = 0011 1111 1000 0000 0000 0000 f) CS/LD Input register- Code of all DACs set to midscale. g) CS/LD Clock SDI = 0011 0000 0000 0000 0000 0000 h) CS/LD Input register- Code of DAC A set to zero code. i) CS/LD Clock SDI = 0100 1111 XXXX XXXX XXXX XXXX j) CS/LD Update all DACs for both Code and Range. k) Alternatively steps i and j could be replaced with LDAC . 2. Using a 32-bit load sequence, load DAC C with bipolar 2.5V and its output at zero volts. Use readback to check Input register contents before updating the DAC output (i.e., before copying Input register contents into DAC register). a) CS/LD (Note that after power-on, the code in Input register is zero) Clock SDI = 0000 0000 0011 0100 1000 0000 0000 0000 b) CS/LD Input register- Code of DAC C set to midscale setting. c) CS/LD Clock SDI = 0000 0000 0010 0100 0000 0000 0000 0100 Data out on SRO = 1000 0000 0000 0000 Verifies that Input register- Code DAC C is at midscale setting. d) CS/LD Input register- Range of DAC C set to Bipolar 2.5V range. e) CS/LD Clock SDI = 0000 0000 1010 0100 xxxx xxxx xxxx xxxx Data Out on SRO = 0000 0000 0000 0100 Verifies that Input register- range of DAC C set to Bipolar 2.5V Range. CS/LD f) CS/LD Clock SDI = 0000 0000 0100 0100 xxxx xxxx xxxx xxxx g) CS/LD Update DAC C for both Code and Range h) Alternatively steps f and g could be replaced with LDAC .
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15
LTC2754 OPERATION
System Offset and Reference Adjustments The LTC2754 has individual offset- and gain- adjust pins (VOSADJX and GEADJX, respectively) for each of its four DACs. Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2754, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps. The offset adjust pins VOSADJX can be used to null unipolar offset or bipolar zero error. The offset-voltage delta is inverted and attenuated such that a 5V control voltage applied to VOSADJX produces VOS = -512 LSB (LTC2754-16) in any output range (assumes a 5V reference voltage at RINX). In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) VOS = -(1/128)VOSADJX [0V to 5V, 2.5V spans] VOS = -(1/64)VOSADJX [0V to 10V, 5V, -2.5V to 7.5V spans] VOS = -(1/32)VOSADJX [10V span] The gain error adjust pins GEADJX can be used to null gain error or to compensate for reference errors. Nominal adjustment range is 512 LSB (LTC2754-16) for a voltage input range of VRINX (i.e., 5V for a 5V reference input). The gain-error delta is non-inverting for positive reference voltages. Note that these pins compensate the gain by altering the inverted reference voltage VREFX. In voltage terms, the VREFX delta is inverted and attenuated by a factor of 128. VREFX = -(1/128)GEADJX The nominal input range of these pins is 5V; other voltages of up to 15V may be used if needed. However, do not use voltages divided down from power supplies; reference-quality, low-noise inputs are required to maintain the performance of which the part is capable. The VOSADJX pins have an input impedance of 1.28M. These pins should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2754. They should be shorted to GND if not used. The GEADJX pins have an input impedance of 2.56M, and are intended for use with fixed reference voltages only. They should be shorted to GND if not used. If the reference inverting resistors are not used for that channel, then GEADJX, RCOMX and RINX should all be shorted to REFX. Power-On Reset and Clear When power is first applied to the LTC2754, all DACs power-up in unipolar 5V mode (S3 S2 S1 S0 = 0000). All internal DAC registers are reset to 0 and the DAC outputs initialize to zero volts. If the part is configured for manual span operation, all four DACs will be set into the pin-strapped range at the first Update command. This allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. When the CLR pin is taken low, a system clear results. The DAC buffers are reset to 0 and the DAC outputs are all reset to zero volts. The Input buffers are left intact, so that any subsequent Update command (including the use of LDAC) restores the addressed DACs to their respective previous states. If CLR is asserted during an instruction, i.e., when CS/LD is low, the instruction is aborted. Integrity of the relevant Input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. The RFLAG pin is used as a flag to notify the system of a loss of data integrity. The RFLAG output is asserted low at power-up, system clear, or if the supply VDD dips below approximately 2V; and stays asserted until any valid Update command is executed.
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16
OPERATION
LSB D14 16-BIT CODE MSB C2 CONTROL WORD ADDRESS WORD 12-BIT CODE C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 0 0 0 4 ZEROS 0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB C2 CONTROL WORD ADDRESS WORD C1 C0 A3 A2 A1 A0 D15
LTC2754-16 (WRITE CODE)
C3
SDI
LTC2754-12 (WRITE CODE)
C3
LTC2754-16 LTC2754-12 (WRITE SPAN) C2 CONTROL WORD ADDRESS WORD C1 C0 A3 A2 A1 A0 0 0 0 0 0 0
C3
0
0
0
0
0
0
S3
S2
S1 SPAN
S0
2754 F02
12 ZEROS
Figure 2. Serial Input Write Sequence
LTC2754
17
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LTC2754
18
24-BIT DATA STREAM 1 2 7 13 14 17 D7 D6 D5 D4 D3 D2 D1 D0 D10 DAC CODE OR DAC SPAN 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D9 D8 D11 A1 A0 D15 D14 D13 D12 21 23 C2 CONTROL WORD ADDRESS WORD 0 0 0 0 0 0 0 C1 C0 A3 A2 10 11 12 18 24 22 16 20 3 4 5 6 8 9 15 19 0 SPAN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S3 S2 S1 S0
2754 F03
CS/LD
OPERATION
SCK
SDI
C3
SRO
Hi-Z
READBACK CODE
SRO
Hi-Z
READBACK SPAN
Figure 3a. 24-Bit Instruction Sequence
32-BIT DATA STREAM
CS/LD 5 6 7 13 14 17 D15 D14 A2 ADDRESS WORD 0 0 0 0 0 D15 D14 D13 D12 D11 D10 A1 A0 A3 0 CONTROL WORD 0 0 0 0 0 0 0 C3 C2 C1 C0 8 9 10 D13 11 12 18 16 15 0 19 20 D12 21 D11 22 D10 23 D9 24 D8 25 D7 26 D6 DAC CODE OR DAC SPAN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 27 D5 28 D4 29 D3 30 D2 31 D1 32 D0
SCK
1
2
3
4
SDI
0
0
0
0
0
8 ZEROS
SRO
Hi-Z
0
0
0
0
0
READBACK CODE Hi-Z SRO 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
0 t1
0
0
0
0
0
0
0
S3
S2
S1 SPAN t2 SCK 17 t3 SDI SRO D15 t9 D15 D14 t4 D14 18
S0
2754 F04
READBACK SPAN
Figure 3b. 32-Bit Instruction Sequence
2754f
LTC2754 OPERATION
SDI
WRITE DATA DAC A
WRITE DATA DAC B
WRITE DATA DAC C
WRITE DATA DAC D
UPDATE ALL DACs
...
SRO
...
READ INPUT DATA REGISTER DAC A
READ INPUT DATA REGISTER DAC B
READ INPUT DATA REGISTER DAC C
READ INPUT DATA REGISTER DAC D
READ DAC DATA REGISTER DAC A
2754 F04
Figure 4. Rolling Readback
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19
LTC2754 APPLICATIONS INFORMATION
Op Amp Selection Because of the extremely high accuracy of the 16-bit LTC2754-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the LTC2754's accuracy when programmed in a unipolar or bipolar output range. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. Tables 4 and 5 can also be used to determine the effects of op amp parameters on the LTC2754-12. However, the results obtained from Tables 4 and 5 are in 16-bit LSBs. Divide these results by 16 to obtain the correct LSB sizing. Table 6 contains a partial list of LTC precision op amps recommended for use with the LTC2754. The easy-to-use design equations simplify the selection of op amps to meet
Table 4. Coefficients for the Equations in Table 5
OUTPUT RANGE 5V 10V 5V 10V 2.5V -2.5V to 7.5V A1 1.1 2.2 2 4 1 1.9 A2 2 3 2 4 1 3 A3 1 0.5 1 0.83 1.4 0.7 1 1 1 0.5 A4 A5 1 1.5 1.5 2.5 1 1.5
Table 5. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
OP AMP VOS1 (mV) INL (LSB) DNL (LSB) UNIPOLAR OFFSET (LSB) BIPOLAR ZERO ERROR (LSB) 5V A3 * VOS1 * 19.8 * V REF 5V IB1 * 0.13 * V REF 0 A4 * VOS2 * 13.1 *
B2
5V 5V 5V VOS1 * 0.82 * V A3 * VOS1 * 13.2 * V VOS1 * 3.2 * V REF REF REF 5V 5V 5V IB1 (nA) IB1 * 0.0003 * V IB1 * 0.00008 * V IB1 * 0.13 * V REF REF REF 16.5k 1.5k AVOL1 (V/V) A1 * A A2 * A 0 VOL1 VOL1 VOS2 (mV) IB2 (mV) AVOL2 (V/V) 0 0 0 0 0 0 0 0 0
() () ()
() () ()
() ()
() ()
REF
(V5V ) ) 5V A4 * (I * 0.13 * ( V )) A4 * ( 66k ) A
REF VOL2
(
UNIPOLAR GAIN ERROR (LSB) 5V VOS1 * 13.2 * V REF 5V IB1 * 0.0018 * V REF 131k A5 * AVOL1 5V VOS2 * 26.2 * VREF 5V IB2 * 0.26 * VREF 131k AVOL2
() () () () () ()
BIPOLAR GAIN ERROR (LSB) 5V VOS1 * 13.2 * V REF 5V IB1 * 0.0018 * V REF 131k A5 * AVOL1 5V VOS2 * 26.2 * VREF 5V IB2 * 0.26 * VREF 131k AVOL2
() () () () () ()
Table 6. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2754 with Relevant Specifications
AMPLIFIER SPECIFICATIONS VOS V 25 50 60 70 75 125 IB nA 2 0.35 0.25 20 10 10 A VOL V/mV 800 1000 1500 4000 5000 2000 VOLTAGE NOISE nV/Hz 10 14 14 2.7 5 5 CURRENT NOISE pA/Hz 0.12 0.008 0.008 0.3 0.6 0.6 SLEW RATE V/s 0.25 0.2 0.16 4.5 22 22 GAIN BANDWIDTH PRODUCT MHz 0.8 0.7 0.75 12.5 90 90 tSETTLING with LTC2755 s 120 120 115 19 2 2 POWER DISSIPATION mW 46 11 10.5/Op Amp 69/Op Amp 117 123/Op Amp
AMPLIFIER LT1001 LT1097 LT1112 (Dual) LT1124 (Dual) LT1468 LT1469 (Dual)
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20
LTC2754 APPLICATIONS INFORMATION
the system's specified error budget. Select the amplifier from Table 6 and insert the specified op amp parameters in Table 5. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Op amp offset will contribute mostly to output offset and gain error, and has minimal effect on INL and DNL. For example, for the LTC2754-16 with a 5V reference in 5V unipolar mode, a 250V op amp offset will cause a 3.3LSB zero-scale error and a 3.3LSB gain error; but only 0.8LSB of INL degradation and 0.2LSB of DNL degradation. While not directly addressed by the simple equations in Tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp's data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers into the VOS and IB equations from Table 5 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 74, "Component and Measurement Advances Ensure 16-Bit DAC Settling Time," offers a thorough discussion of 16-bit DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2754 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2754 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference's output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit's apparent INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients.
Table 7. Partial List of LTC Precision References Recommended for Use with the LTC2754 with Relevant Specifications
REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 LT1790A-2.5 LTC6652A-2.048 LTC6652A-2.5 LTC6652A-3 LTC6652A-3.3 LTC6652A-4.096 LTC6652A-5 INITIAL TOLERANCE 0.05% 0.05% 0.075% 0.05% 0.05% TEMPERATURE DRIFT 5ppm/C 5ppm/C 10ppm/C 10ppm/C 5ppm/C 0.1Hz to 10Hz NOISE 12VP-P 3VP-P 20VP-P 12VP-P 2.1ppmP-P 2.1ppmP-P 2.1ppmP-P 2.2ppmP-P 2.3ppmP-P 2.8ppmP-P
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21
LTC2754 APPLICATIONS INFORMATION
As precision DAC applications move to 16-bit and higher performance, reference output voltage noise may contribute a dominant share of the system's noise floor. This in turn can degrade system dynamic range and signal-tonoise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references, like the LT1236, produce low output noise in the 0.1Hz to 10Hz region, well below the 16-bit LSB level in 5V or 10V full-scale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise. Grounding As with any high resolution converter, clean grounding is important. A low impedance analog ground plane and star grounding techniques should be used. IOUT2X must be tied to the star ground with as low a resistance as possible. When it is not possible to locate star ground close to IOUT2, a low resistance trace should be used to route this pin to star ground. This minimizes the voltage drop from this pin to ground caused by the code-dependent current flowing to ground. When the resistance of this circuit board trace becomes greater than 1, a force/sense amplifier configuration should be used to drive this pin (see Figure 5). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC2754-16. Layout Figures 6, 7, 8, and 9 show the layout for the LTC2754 evaluation board, DC1546. This shows how to route the digital signals around the device without interfering with the reference and output op amps. Complete demo board documentation is available in the DC1546 "Quick Start Guide."
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22
LTC2754 APPLICATIONS INFORMATION
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE IOUT2 3, 12, 29, 38 200 200 IOUT2 1000pF 3 1 ZETEX* BAT54S 2 3
2
2
6
6 1 ZETEX BAT54S 2 3
LT1001 3
*SCHOTTKY BARRIER DIODE VREF 5V ROFSA 50 RINA 2 3 LTC2754-16 49 RFBA 15pF
1/2 LT1469 2 RCOMA 150pF 51 REFA DAC B 52
DAC A 3 IOUT2A 47 VOSADJA 3
- + - + - +
2754 F05
DAC C
DAC D
Figure 5. Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier.
+
-
1
GEADJA 1
48 IOUT1A
+
2
LT1468
-
- + - +
1/2 LT1469
1
VOUTA
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23
LTC2754 APPLICATIONS INFORMATION
2754 F06
Figure 6. LTC2754 Evaluation Board DC1546. Layer 1, Top Layer (Component Side)
2754 F07
Figure 7. LTC2754 Evaluation Board DC1546. Layer 2, GND Plane
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24
LTC2754 APPLICATIONS INFORMATION
2754 F08
Figure 8. LTC2754 Evaluation Board DC1546. Layer 3, Power Traces
2754 F09
Figure 9. LTC2754 Evaluation Board DC1546. Layer 4, Bottom Layer (Solder Side)
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25
LTC2754 TYPICAL APPLICATION
Digitally Controlled Offset and Gain Trim Circuit. Powering VDD from LT1236 Ensures Quiet Supply
150pF V+ 8 4 V- 10 VDD 30 31 CS1 SDI SCK SDO CS2 5V 0.1F 0.1F 11 10k REF 7 CS/LD 8 SCK 9 SDI 1 VCC 2 3 4 5 12 13 14 15 T0 ADDITIONAL OFFSET ADJUST CIRCUITS LTC2754 VOSADJB 46 5 6 7 8 36 39 41 2 52 42 43 V+ 8 4 V- 44 51 REFA 50 ROFSA 49 RFBA 48 3 6 5 V+ 8 4 V VOSADJA 47
-
150pF
7
5 5V V+ 2 10F IN 6 OUT LT1236-5 5 TRIM GND 4 CLR RFLAG CS/LD SDI SCK 10F 10k 10k 10k 0.1F
3
RINB RRCOMB RINA
RCOMA REFB
ROFSB RFBB
IOUT1A IOUT2A
TO LT1991 27pF
LDAC
IOUT1B IOUT2B
38
3
TO LT1991 27pF
32 35 34 33
M-SPAN S2 S1
IOUT1C IOUT2C
29
5
T0 ADDITIONAL GAIN ADJUST CIRCUITS
VOSADJC S0
21
TO LT1991
16 IOUT1D IOUT2D VOSADJD V+ 7 8 9 10 1 2 3 50k M9 M3 M1 P1 P3 P9 150k 50k 150k 4F 450k 450k 450k LT1991 TO LT1991s 5V V+ 8 4 LT1469 V- V+ 8 150pF GEADJA GEADJB GEADJC GEADJD GND GND GND GND SROGND RINC RCOMC RIND RCOMD REFC ROFSC RFBC REFD ROFSD RFBD 1 40 27 14 4 11 37 53 9 28 26 13 15 25 24 23 16 17 18
12 20
3
450k 4F REF 5
3
3
4 V- V+ 7 8 9 10 1 2 3 50k M9 M3 M1 P1 P3 P9 150k 50k 150k 4F 450k 450k 450k LT1991
OUT 6 450k 4F REF 5
4 V-
26
+ -
+ -
OUT 6
2
150pF
2
7
4 LT1469 V-
2754 TA02
+ -
19
2
+ -
VOUTA VOUTB VOUTC V LTC2636 OUTD VOUTE VOUTF 10 VOUTG CLR 6 LDAC VOUTH GND
22
6
+ -
SRO
45
2
+ -
+ -
+ -
6
2
1
27pF
7
VOUTD
V+ 8 4 V
-
7
VOUTB
V+ 8
7
VOUTC
4 LT1469 V- 27pF
V+ 8
1
VOUTA
4 LT1469 V-
+ - + -
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LTC2754 PACKAGE DESCRIPTION
UKG Package 52-Lead Plastic QFN (7mm x 8mm)
(Reference LTC DWG # 05-08-1729 Rev O)
7.50 0.05 6.10 0.05 5.50 REF (2 SIDES) 0.70 0.05
6.45 0.05 6.50 REF 7.10 0.05 8.50 0.05 (2 SIDES)
5.41 0.05
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 7.00 0.10 (2 SIDES) 0.75 0.05 0.00 - 0.05 R = 0.115 TYP 5.50 REF (2 SIDES) 51 52 0.40 1 2 PIN 1 NOTCH R = 0.30 TYP OR 0.35 45 C CHAMFER 0.10
PIN 1 TOP MARK (SEE NOTE 6)
6.45 0.10 8.00 0.10 (2 SIDES) 6.50 REF (2 SIDES)
5.41 0.10
TOP VIEW 0.200 REF 0.00 - 0.05
R = 0.10 TYP
(UKG52) QFN REV O 0306
0.25 0.05 0.50 BSC BOTTOM VIEW--EXPOSED PAD
0.75
0.05
SIDE VIEW NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC2754 RELATED PARTS
PART NUMBER LT1027 LT1236A-5 LT1468 LT1469 LTC1588/LTC1589/ LTC1592 LTC1591/LTC1597 LTC2704 LTC2751 LTC2753 LTC2755 DESCRIPTION Precision Reference Precision Reference 16-Bit Accurate Op-Amp Dual 16-Bit Accurate Op-Amp Serial 12-/14-/16-Bit IOUT Single DAC Parallel 14-/16-Bit IOUT Single DAC Serial 12-/14-/16-Bit VOUT Quad DACs Parallel 12-/14-/16-Bit IOUT SoftSpan Single DAC Parallel 12-/14-16-Bit IOUT SoftSpan Dual DACs Parallel 12-/14-/16-Bit IOUT SoftSpan Quad DACs COMMENTS 1ppm/C Maximum Drift 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise 90MHz GBW, 22V/s Slew Rate 90MHz GBW, 22V/s Slew Rate Software-Selectable (SoftSpan) Ranges, 1LSB INL, DNL, 16-Lead SSOP Package Integrated 4-Quadrant Resistors Software-Selectable (SoftSpan) Ranges, Integrated Amplifiers, 1LSB INL 1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 5mm x 7mm QFN-38 Package 1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 7mm x 7mm QFN-48 Package 1LSB INL, DNL, Software-Selectable (SoftSpan) Ranges, 9mm x 9mm QFN-64 Package
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28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0609 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2009

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